/** ###################################################################
**     Filename  : Rtl.C
**     Project   : CyberPark
**     Processor : MC9S12XS128MAL
**     Compiler  : CodeWarrior HCS12X C Compiler
**     Date/Time : 2011-7-31, 23:02
**     Contents  :
**         User source code
**
**     (c) Copyright UNIS, a.s. 1997-2008
**     UNIS, a.s.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : info@processorexpert.com
** ###################################################################*/

/* MODULE Rtl */
#include "Rtl.h"
U16 RtlLimitU16(U16 number, U16 min, U16 max)
{
	if (number < min) {
		number = min;
	} else if (number > max) {
		number = max;
	}
	return number;
}

S16 RtlLimitS16(S16 number, S16 min, S16 max)
{
	if (number < min) {
		number = min;
	} else if (number > max) {
		number = max;
	}
	return number;
}

S16 RtlAbsS16(S16 number)
{
	if (number >= 0) {
		return number;
	} else {
		return -number;
	}
}

S16 RtlSquareS16(S16 number)
{
	return number * number;
}

S16 RtlScaleS16(S16 x, S16 l0, S16 h0, S16 l, S16 h)
{
	return (S16)(((S32)x - (S32)l0) * ((S32)h - (S32)l) / ((S32)h0 - (S32)l0) + l);
}

void SetBusCLK_80M(void)
{  
    CLKSEL=0X00;    //disengage PLL to system
    PLLCTL_PLLON=1;   //turn on PLL
    SYNR =0xc0 | 0x09;                       
    REFDV=0x80 | 0x01;
    POSTDIV=0x00;       //pllclock=2*osc*(1+SYNR)/(1+REFDV)=160MHz;
    _asm(nop);          //BUS CLOCK=80M
    _asm(nop);
    while(!(CRGFLG_LOCK==1));   //when pll is steady ,then use it;
    CLKSEL_PLLSEL =1;          //engage PLL to system;
    return;
}




/* END Rtl */
